User manual CADENCE DESIGN SYSTEMS INCISIVE VERIFICATION IP PORTFOLIO OVERVIEW
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Manual abstract: user guide CADENCE DESIGN SYSTEMS INCISIVE VERIFICATION IP PORTFOLIOOVERVIEW
Detailed instructions for use are in the User's Guide.
[. . . ] INC I S I V E V E R I F I C AT I O N I P POR T F O L I O
OVER VIEW
INCISIVE VIP PORTFOLIO
SINGLE LICENSE INCLUDES: AMBA® AHB AMBA APB AMBA AXI ATAPI CAN DDR2/DDR3 Ethernet Ethernet 40/100G FibreChannel HDMI IC
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The Cadence® Incisive® Verification IP (VIP) Portfolio is a family of Universal Verification Components (UVCs) and AssertionBased VIP that enables metric-driven verification of standard SoC interfaces.
HIGHLIGHTS
· Proveninmorethan2, 000projects · Conformstoindustry-standardOpenVerification Methodology (OVM) · SupportsSystemVerilog(IEEE-1800)ande(IEEE-1647) languages · Includesprotocol-specificComplianceManagement System (CMS)
MIPI SLIMbusSM MIPI UniProSM OCP OCP 3. 0 PCI PCI Express PCI Express Gen3 SAS SAS 6Gb/s SATA SATA 6Gb/s SDIO SDXC Serial RapidIO SPI-4 USB USB 3. 0
BREADTH
Support for 30+ protocols Single portfolio license
CONVENIENCE
One common interface One common license One common architecture
DEPTH
Constrained-random architecture Metric-driven environment Compliance Management System
QUALITY & PRODUCTIVITY
Superior bug detection Schedule predictability Embedded protocol expertise
JTAG LIN MIPI® CSI-2 MIPI DigRFSM MIPI D-PHY MIPI DSI
STANDARD
OVM compliant Multi-language support: SystemVerilog and e
COMPATIBILITY
Collaboration across projects Open, multi-vendor standard
FOCUS ON VERIFICATION
IncisiveVerificationIPisindependentlycreatedandtestedagainstexternaldesignIPsourcesto providefullyobjectivevalidation. ThisfocuspreventsthebugtransferthatcanoccurwhendesignIP and verification IP are co-developed.
VERIFYING HOST MODULES
Incisive Universal Verification Components (UVCs) assist in the verificationofDUThosts(masters, transmitters, etc. )byproviding active device components to receive data. [. . . ] plan is displayed and any coverage gaps are clearly identified. Theverificationengineerthenadjuststhetestgeneration constraintstofocusadditionaltestsequencesonthecoverage points of interest. Projectmanagementisfacilitatedthroughvariousreportsand chartswhichmeasureprogressvs. plan. Earlywarningisthus providedforscheduledeviationsandresourcelimitations.
COMPLIANCE MANAGEMENT SYSTEM
Compliance Coverage Model Compliance Checks and Metrics
GAP ANALYSIS EXAMPLE
PROTOCOL COMPLIANCE AND THE VERIFICATION PLAN
ProtocolcompliancestartswiththeVerificationPlan(vPlan). All verificationobjectivesarecapturedinthevPlanandcorrelated to the protocol specification on a paragraph by paragraph basis. Alibraryofconstrained-randomtestsequencesthenstimulates thedesign-under-testwithmultipleparametercombinationsfor eachcoveragepointofinterest. Thisresultsinmoreexhaustive verificationthanrunningalargesetofnon-randomizedvalidation tests.
Coverage Holes Identified
www. cadence. com
INCISIVE VIP POR TFOLIO
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PORTFOLIO LICENSING
Incisive UVCs are licensed collectively as the Incisive VIP Portfolio. Consequently, asinglelicenseenablesanyoneof theprotocolsinasinglesimulationrun. ThispreservesyourVIP investmentasprojectneedschange. Also, newprotocolsare addedtotheportfolioastheybecomeavailable, furtherincreasingtheportfolio'svalue.
ACCELERATION AND EMULATION
Cadence provides additional VIP for protocol verification in hardwareaccelerationandemulationenvironments, suchas theIncisivePalladium® and Xtreme® Systems. Transaction-Based VIPisofferedtosupporttheSystemC® testbenches associated withhardwareacceleration. High-leveltransactionsefficiently communicatewiththeDUTrunningintheaccelerator. Inthis environment, youcanachievesimulationspeedsof100xthe performanceofsoftwaresimulators. Cadence SpeedBridge®Adaptorsareusedforprotocolverificationduringhardwareemulation. Thesecircuitcardsprovide thehigh-speedstimulusrequiredtounleashtheperformance ofemulation. UsingSpeedBridgeAdaptorsandthePalladium System, youcanachievesimulationspeeds10, 000xfasterthan softwaresimulation.
"We've determined that 90% of the risk is in the chip's interfaces. If we design the interfaces incorrectly, it doesn't matter if we get the rest of the chip right. This is especially true with PCI Express since it's such a complex protocol. The bottom line for us is that the choice we made to go with proven IP that's easy to get up and running is just good, solid common sense. "
Jim O'Connor, VP of Engineering iVivity
LEARN MORE
· Aresourcelibraryplussupportandtraininginformationare availableat:http://www. cadence. com/products/fv/ verification_ip · Hands-ondemosofIncisiveVIPareavailableattheXuropa onlinecommunity:www. xuropa. com/cadence · Call1. 800. 746. 6223tospeakwitharepresentative
© 2009 Cadence Design Systems, Inc. [. . . ] SystemC is a registered trademark of the Open SystemC Initiative, Inc. [. . . ]
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