User manual DCS 972
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Manual abstract: user guide DCS 972
Detailed instructions for use are in the User's Guide.
[. . . ] dCS 972
Digital to Digital Converter
User Manual
Software version 2. 3x January 2001
© 1997, 1999, 2000, 2001 dCS Ltd
All rights reserved. Reproduction of this manual in any manner whatsoever, without the written permission of dCS1 is strictly forbidden. Information contained in this manual is subject to change without notice, and whilst it is checked for accuracy, no liabilities can be accepted for errors.
1
dCS Ltd is Data Conversion Systems Ltd. 2072115
dCS 972 User Manual dCS Ltd
Manual for Software Version 2. 3x January 2001
Manual part no: DOC1241102C2 Contact dCS on + 44 1799 531 999
Page 2
Document No: OS-MA-A0124-110. 2C2
(inside the UK replace + 44 with 0)
email to: more@dcsltd. co. uk web site: www. dcsltd. co. uk
dCS 972 User Manual dCS Ltd
Manual for Software Version 2. 3x January 2001
Product Features
Formats DSD, and PCM from 192 kS/s down to 11. 025 kS/s PCM data formats supported are: AES/EBU (XLR), Dual AES (XLR), SPDIF (Phono, Toslink and BNC) and SDIF-2 DSD data formats supported are SDIF-2 and SDIF-3 Converts double speed (88. 2 & 96 kS/s) AES3, SPDIF or SDIF-2 into Dual (2 wire) AES3 and vice-versa. [. . . ] Format Conversion: Audio Input Select: Sync Source: Input Frequency: Output Frequency: Output Mode: AES Message Edit: SPDIF Message Edit: On Dual AES Audio Input11 96 kS/s 96 kS/s Normal Professional On, Non-Audio Off Mode: Stereophonic Professional On, Non-Audio Off, Copy Permit On Format: 2-Ch Gen Format
11
If using a dCS 992 Master Clock, set the Sync Source to AES when using an AES Clock output or Word Clock when using a SDIF-2 output. Ensure the clock signal is connected to the appropriate input on the dCS 972.
Manual part no: DOC1241102C2 Contact dCS on + 44 1799 531 999
Page 47
SPDIF Outputs
SPDIF Inputs
Document No: OS-MA-A0124-110. 2C2
(inside the UK replace + 44 with 0)
email to: more@dcsltd. co. uk web site: www. dcsltd. co. uk
dCS 972 User Manual dCS Ltd
Manual for Software Version 2. 3x January 2001
Upsampling a CD
24 bit / 96kS/s Dual AES output to 24/96 DAC
AES1
PUSH
AES2
PUSH
AES CLK
PUSH
AES1
AES2
AES CLK
In
SDIF-2 Inputs
CH1
CH2
CLK
AES / EBU Inputs
AES / EBU Outputs
Out
Remote
MAINS FUSE 2A(T) ON
OFF
SPDIF1
SPDIF2
SPDIF3
SYNC IN
CH1
CH2
CLK
SDIF-2 Outputs
16bit / 44. 1kS/s
DIGITAL OUT
AES REF
PUSH
WORDCLOCK IN
L R
Hand Crafted by The Red Hot CD Player Co.
Figure 5 Upsampling a CD to 24/96 (or 24/192) The dCS 972 converts a 44. 1 kS/s 16 bit SPDIF input (or AES3 input, dotted) to a Dual 96 kS/s 24 bit signal available from AES A & B outputs. There is no information added in the process, although you may wish to check theory here. do this: do this: do this: Connect a source of CD material to the SPDIF 1 input on the dCS 972. Output Dual AES data from both AES A and AES B to a DAC of your choice (dCS Elgar, dCS Delius or dCS 954).
Sample Rate Conversion settings: The settings below are preloaded into Store 3 by dCS, although they may be overwritten. Sample Rate Conversion: Audio Input Select: Sync Source: Input Frequency: Output Frequency: Output Mode: Filter: Output Wordlength: Noise Shaping: Dither: Detect Silence: AES Message Edit: SPDIF Message Edit: On SPDIF 1 Audio Input Auto (44. 1 kS/s) 96 kS/s Dual AES Filter 2 24 Off Off Off Professional On, Non-Audio Off, Mode: Stereophonic Professional On, Non-Audio Off, Copy Permit On Format: 2-Ch Gen Format
Manual part no: DOC1241102C2 Contact dCS on + 44 1799 531 999
Page 48
SPDIF Outputs
SPDIF Inputs
Document No: OS-MA-A0124-110. 2C2
(inside the UK replace + 44 with 0)
email to: more@dcsltd. co. uk web site: www. dcsltd. co. uk
dCS 972 User Manual dCS Ltd
Manual for Software Version 2. 3x January 2001
General Sample Rate Conversion and Distribution
From ANY format: AES, SPDIF, Toslink, SDIF-2 at any sample rate: 11. 025k / 12k / 16k / 22. 05k / 24k / 32k / 44. 1k / 48k / 88. 2k or 96kS/s or Dual AES at 88. 2k / 96k / 176. 4k or 192kS/s or DSD
AES1
PUSH
AES2
PUSH
AES CLK
PUSH
AES1
AES2
AES CLK
In
SDIF-2 Inputs
CH1
CH2
CLK
AES / EBU Inputs
AES / EBU Outputs
Out
Remote
MAINS FUSE 2A(T) ON
OFF
SPDIF1
SPDIF2
SPDIF3
SYNC IN
CH1
CH2
CLK
SDIF-2 Outputs
To ALL formats: AES, SPDIF, Toslink, SDIF-2 at any sample rate: 11. 025k / 12k / 16k / 22. 05k / 24k / 32k / 44. 1k / 48k / 88. 2k or 96kS/s or Dual AES at 88. 2k / 96k / 176. 4k or 192kS/s or DSD
Figure 6 General Sample rate Conversion The dCS 972 converts any one of 12 sampling frequencies in any format to any of the 12 sampling frequencies in ALL formats: 3 AES, 2 electrical SPDIF, optical SPDIF or SDIF-2 outputs. Most frequency combinations (including all the primary ones) are accommodated in one pass - see the table in Table 2 One Pass and Two Pass Conversions on page 26. For best results, the unit should be slaved to the active input, the AES Clock Input or the SDIF-2 Word Clock Input. do this: Connect any digital audio source of any word length between 8 and 24 bits, using single or dual wire AES to the AES inputs, or using single or double speed SDIF-2 to the SDIF-2 inputs, or using single wire SPDIF to the appropriate SPDIF input. Output via any of the outputs
do this: do this:
Sample Rate Conversion settings: Sample rate Conversion: Audio Input Select: Output Mode: On Any, even including Dual AES if the Input 12 Frequency is any of 192 kS/s, 176. 4 kS/s , 96 kS/s or 88. 2 kS/s. Normal or Dual AES may be selected if the Output Frequency is set to 96 kS/s or 88. 2 kS/s. Any.
Other settings:
12
It has to be Dual AES for 192 kS/s or 176. 4 kS/s
Manual part no: DOC1241102C2 Contact dCS on + 44 1799 531 999
Page 49
SPDIF Outputs
SPDIF Inputs
Document No: OS-MA-A0124-110. 2C2
(inside the UK replace + 44 with 0)
email to: more@dcsltd. co. uk web site: www. dcsltd. co. uk
dCS 972 User Manual dCS Ltd
Manual for Software Version 2. 3x January 2001
PCM to DSD
From PCM in ANY format: AES, SPDIF, Toslink, SDIF-2 or Dual AES at 88. 2k / 96k / 176. 4k or 192kS/s
AES1
PUSH
AES2
PUSH
AES CLK
PUSH
AES1
AES2
AES CLK
In
SDIF-2 Inputs
CH1
CH2
CLK
AES / EBU Inputs
AES / EBU Outputs
Out
Remote
MAINS FUSE 2A(T) ON
OFF
SPDIF1
SPDIF2
SPDIF3
SYNC IN
CH1
CH2
CLK
SDIF-2 Outputs
DSD out
Figure 7 PCM to DSD conversion The dCS 972 converts PCM to DSD (including 176. 4 kS/s to DSD) using the arrangement given below: do this: Connect any digital audio source of any Word Length between 8 and 24 bits, using single or dual wire AES to the AES inputs, or using single or double speed SDIF-2 to the SDIF-2 inputs, or using single wire SPDIF to the appropriate SPDIF input, and select input accordingly. Output via the SDIF-2 connectors, two data cables and one word clock.
do this: do this:
Sample Rate Conversion settings: The settings are preloaded in store 10 by dCS, although they may be overwritten. Sample Rate Conversion: On Audio Input Select: Any, even including Dual AES if the Input Frequency is any of 192 kS/s, 176. 4 kS/s, 96 kS/s or 88. 2 kS/s. Sync Source: Any Input Frequency: Any Output Frequency: n/a Output Mode: DSD Filter: Any Output Wordlength: n/a Noise Shaping: n/a Dither: n/a Detect Silence: n/a
Manual part no: DOC1241102C2 Contact dCS on + 44 1799 531 999
Page 50
SPDIF Outputs
SPDIF Inputs
Document No: OS-MA-A0124-110. 2C2
(inside the UK replace + 44 with 0)
email to: more@dcsltd. co. uk web site: www. dcsltd. co. uk
dCS 972 User Manual dCS Ltd
Manual for Software Version 2. 3x January 2001
Using a Master Clock
DIGITAL OUT AES REF
PUSH
WORDCLOCK IN
L R
Hand Crafted by The Red Hot CD Player Co.
16bit / 44. 1kS/s
AES 1
more@dcsltd. co. uk
AES 2
AES 3
AES 4 Wordclock Outputs
1
2
3
4
5
6
In
Mains
Fuse (2AT)
On
Off
AES/EBU Outputs
7
8
9
10
11
12
External Sync
Loop Remote Out
dCS 992 96kS/s Master Clock AES REF to other system components Wordclock to other system components
AES1
PUSH
AES2
PUSH
AES CLK
AES1
AES2
AES CLK
In
SDIF-2 Inputs
PUSH
AES / EBU Inputs
AES / EBU Outputs
CH1
CH2
CLK
Out
Remote
MAINS FUSE 2A(T) ON
OFF
SPDIF1
SPDIF2
SPDIF3
SYNC IN
CH1
CH2
CLK
SDIF-2 Outputs
Dual AES up to 24 bit / 192kS/s
CH1(L)
CH2(R)
Sensitivity
Reference In
PUSH
Reference Out
AES1
PUSH
AES2
PUSH
AES3
PUSH
AES4
PUSH
CH1
SPDIF Outputs
CH2 In
SPDIF Inputs
MAINS FUSE 2A(T) ON OFF
CH1(L) CH2(R) In
SDIF-2/DSD Remote Out Out 75R Clk
Analogue
Digital I/O
Balanced Analogue Outputs
Unbalanced Analogue Outputs
dCS 954 24/192 DAC (or Elgar or Delius)
Figure 8 Using a Master Clock If a Master Clock such as a dCS 992 is available and the driving source is locked to it, the dCS 972 may be locked to it. Either: do this: connect the Master Clock to the AES CLK Input and select AES as the Sync Source, or: do this: connect the Master Clock to the SDIF-2 CLK Input and select Word Clock as the Sync Source. Since the Output Frequency of the dCS 972 is different to the Master Clock frequency, the DAC would be unable to lock to the data from the dCS 972 if it were sync'ed to the Master Clock. So, slave the DAC to the dCS 972, NOT to the Master Clock.
IMPORTANT!
Manual part no: DOC1241102C2 Contact dCS on + 44 1799 531 999
Page 51
Document No: OS-MA-A0124-110. 2C2
(inside the UK replace + 44 with 0)
email to: more@dcsltd. co. uk web site: www. dcsltd. co. uk
dCS 972 User Manual dCS Ltd
Manual for Software Version 2. 3x January 2001
Multi-channel Sample Rate Conversion bit aligned sources
96kS/s Ch1 & 2
AES1
P USH
AES2
P USH
AES CLK
P USH
AES1 SDIF-2 Inputs CH1 CH2 CLK
AES2
AES CLK
In Remote MAINS FUSE 2A(T) ON
AES / EBU Inputs
AES / EBU Outputs
Out
OFF
SPDIF1 SPDIF Inputs
SPDIF2
SPDIF3
SYNC IN
CH1
CH2
CLK SPDIF Outputs
SDIF-2 Outputs
96kS/s Ch3 & 4
AES1
P USH
AES2
P USH
AES CLK
P USH
AES1 SDIF-2 Inputs CH1 CH2 CLK
AES2
AES CLK
In Remote MAINS FUSE 2A(T) ON
AES / EBU Inputs
AES / EBU Outputs
44. 1kS/s SOURCE
Out
OFF
SPDIF1 SPDIF Inputs
SPDIF2
SPDIF3
SYNC IN
CH1
CH2
CLK SPDIF Outputs
SDIF-2 Outputs
96kS/s Ch5 & 6
AES1
P USH
AES2
P USH
AES CLK
P USH
AES1 SDIF-2 Inputs CH1 CH2 CLK
AES2
AES CLK
In Remote MAINS FUSE 2A(T) ON
AES / EBU Inputs
AES / EBU Outputs
Out
OFF
SPDIF1 SPDIF Inputs
SPDIF2
SPDIF3
SYNC IN
CH1
CH2
CLK SPDIF Outputs
SDIF-2 Outputs
96kS/s Ch7 & 8
AES1
P USH
AES2
P USH
AES CLK
P USH
AES1 SDIF-2 Inputs CH1 CH2 CLK
AES2
AES CLK
In Remote
AES / EBU Inputs
AES / EBU Outputs
Out
SPDIF3
CH2
CLK
Figure 9 Multi-channel Sample Rate Conversion with bit aligned source
If the source data is bit aligned (for example, from a multitrack recorder) up to four or five dCS 972's may be set to operate synchronously using the sync link connections shown above, from one unit's AES CLK Output to the next unit's AES CLK Input. The top unit will set up as a master, the other ones will set up as slaves. See section Multiple Channel Sync'ing, page 68 for how aligned is bit aligned. These are set up, for PCM in to DSD out, in Store 11, and for PCM in to 96 kS/s out in Store 12, by dCS. You can overwrite them.
Manual part no: DOC1241102C2 Contact dCS on + 44 1799 531 999
Page 52
Document No: OS-MA-A0124-110. 2C2
(inside the UK replace + 44 with 0)
email to: more@dcsltd. co. uk web site: www. dcsltd. co. uk
dCS 972 User Manual dCS Ltd
Manual for Software Version 2. 3x January 2001
Multi-channel Sample Rate Conversion Using a Master Clock
TO RECORDER (44. 1kS/s WORDCLOCK)
AES 1
more@dcsltd. co. uk
AES 2
AES 3
AES 4 Wordclock Outputs
1
2
3
4
5
6
In
Mains
Fuse (2AT)
On
Off
AES/EBU Outputs
7
8
9
10
11
12
External Sync
Loop Out
Remote
A
AES1
PUSH
dCS 992 Master Clock
AES2
PUSH
96kS/s Ch1 & 2
AES CLK
PUSH
AES1
AES2
AES CLK
In
SDIF-2 Inputs
CH1
CH2
CLK
AES / EBU Inputs
AES / EBU Outputs
Out
Remote
MAINS FUSE 2A(T) ON
OFF
SPDIF1
SPDIF2
SPDIF3
SYNC IN
CH1
CH2
CLK
SDIF-2 Outputs
SPDIF Outputs
SPDIF Inputs
96kS/s Ch3 & 4
AES1
PUSH
AES2
PUSH
AES CLK
PUSH
AES1
AES2
AES CLK
In
SDIF-2 Inputs
CH1
CH2
CLK
AES / EBU Inputs
AES / EBU Outputs
44. 1kS/s SOURCE
Out
Remote
MAINS FUSE 2A(T) ON
OFF
SPDIF1
SPDIF2
SPDIF3
SYNC IN
CH1
CH2
CLK
SDIF-2 Outputs
SPDIF Outputs
SPDIF Inputs
96kS/s Ch5 & 6
AES1
PUSH
AES2
PUSH
AES CLK
PUSH
AES1
AES2
AES CLK
In
SDIF-2 Inputs
CH1
CH2
CLK
AES / EBU Inputs
AES / EBU Outputs
Out
Remote
MAINS FUSE 2A(T) ON
OFF
SPDIF1
SPDIF2
SPDIF3
SYNC IN
CH1
CH2
CLK
SDIF-2 Outputs
SPDIF Outputs
SPDIF Inputs
96kS/s Ch7 & 8
AES1
PUSH
AES2
PUSH
AES CLK
PUSH
AES1
AES2
AES CLK
In
SDIF-2 Inputs
CH1
CH2
CLK
AES / EBU Inputs
AES / EBU Outputs
Out
SPDIF3
CH2
CLK
Figure 10 Multi-channel Sample Rate Conversion with Master Clock
You can use a dCS 992 Master Clock to sync up the source and be the master. [. . . ] Level in decibels, referred to a 0. 775V rms sine wave, with no external loading (u = unloaded). The level of 0. 775V is derived from the older dBm, for which the reference level is 1mW of signal power into a 600 termination from an output with 600 source impedance. Level in decibels, referred to a 1. 0V rms sine wave, with no external loading. This replaces kHz which is technically incorrect when referring to sample rates. [. . . ]
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