Detailed instructions for use are in the User's Guide.
[. . . ] TE X AS I NS TRUM E NTS - P RO DUCTION D ATA
Stellaris® LM3S1332 Microcontroller
D ATA SH E E T
D S -LM 3S 1332 - 7 7 8 7
C opyri ght © 2007-2010 Texas Instruments Incorporated
Copyright
Copyright © 2007-2010 Texas Instruments Incorporated All rights reserved. Stellaris and StellarisWare are registered trademarks of Texas Instruments Incorporated. ARM and Thumb are registered trademarks and Cortex is a trademark of ARM Limited. Products conform to specifications per the terms of Texas Instruments standard warranty. [. . . ] To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. ADC Module Present When set, indicates that the ADC module is present.
16
ADC
RO
1
15:12
MINSYSDIV
RO
0x3
System Clock Divider Minimum 4-bit divider value for system clock. See the RCC register for how to change the system clock divisor using the SYSDIV bit. Value Description 0x3 Specifies a 50-MHz CPU clock with a PLL divider of 4.
11:10
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Max ADC Speed Indicates the maximum rate at which the ADC samples data. Value Description 0x1 250K samples/second
9:8
MAXADCSPD
RO
0x1
7
MPU
RO
1
MPU Present When set, indicates that the Cortex-M3 Memory Protection Unit (MPU) module is present. See the "Cortex-M3 Peripherals" chapter in the Stellaris Data Sheet for details on the MPU.
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System Control
Bit/Field 6
Name HIB
Type RO
Reset 1
Description Hibernation Module Present When set, indicates that the Hibernation module is present.
5
TEMPSNS
RO
1
Temp Sensor Present When set, indicates that the on-chip temperature sensor is present.
4
PLL
RO
1
PLL Present When set, indicates that the on-chip Phase Locked Loop (PLL) is present.
3
WDT
RO
1
Watchdog Timer Present When set, indicates that a watchdog timer is present.
2
SWO
RO
1
SWO Trace Port Present When set, indicates that the Serial Wire Output (SWO) trace port is present.
1
SWD
RO
1
SWD Present When set, indicates that the Serial Wire Debugger (SWD) is present.
0
JTAG
RO
1
JTAG Present When set, indicates that the JTAG debugger interface is present.
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Stellaris® LM3S1332 Microcontroller
Register 15: Device Capabilities 2 (DC2), offset 0x014
This register provides a list of features available in the system. The Stellaris family uses this register format to indicate the availability of the following family features in the specific device: Analog Comparators, General-Purpose Timers, I2Cs, QEIs, SSIs, and UARTs. The format of this register is consistent with the RCGC1, SCGC1, and DCGC1 clock control registers and the SRCR1 software reset control register.
Device Capabilities 2 (DC2)
Base 0x400F. E000 Offset 0x014 Type RO, reset 0x070F. 0013
31 30 29 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 28 27 26 COMP2 RO 1 10 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 25 COMP1 RO 1 9 24 COMP0 RO 1 8 RO 0 7 23 22 21 20 19 TIMER3 RO 0 4 SSI0 RO 1 RO 1 3 reserved RO 0 RO 0 18 TIMER2 RO 1 2 17 TIMER1 RO 1 1 UART1 RO 1 16 TIMER0 RO 1 0 UART0 RO 1
reserved RO 0 6 RO 0 5
Bit/Field 31:27
Name reserved
Type RO
Reset 0
Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Analog Comparator 2 Present When set, indicates that analog comparator 2 is present.
26
COMP2
RO
1
25
COMP1
RO
1
Analog Comparator 1 Present When set, indicates that analog comparator 1 is present.
24
COMP0
RO
1
Analog Comparator 0 Present When set, indicates that analog comparator 0 is present.
23:20
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Timer 3 Present When set, indicates that General-Purpose Timer module 3 is present.
19
TIMER3
RO
1
18
TIMER2
RO
1
Timer 2 Present When set, indicates that General-Purpose Timer module 2 is present.
17
TIMER1
RO
1
Timer 1 Present When set, indicates that General-Purpose Timer module 1 is present.
16
TIMER0
RO
1
Timer 0 Present When set, indicates that General-Purpose Timer module 0 is present.
15:5
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation.
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System Control
Bit/Field 4
Name SSI0
Type RO
Reset 1
Description SSI0 Present When set, indicates that SSI module 0 is present.
3:2
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. UART1 Present When set, indicates that UART module 1 is present.
1
UART1
RO
1
0
UART0
RO
1
UART0 Present When set, indicates that UART module 0 is present.
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Stellaris® LM3S1332 Microcontroller
Register 16: Device Capabilities 3 (DC3), offset 0x018
This register provides a list of features available in the system. The Stellaris family uses this register format to indicate the availability of the following family features in the specific device: Analog Comparator I/Os, CCP I/Os, ADC I/Os, and PWM I/Os.
Device Capabilities 3 (DC3)
Base 0x400F. E000 Offset 0x018 Type RO, reset 0xBF07. 37C0
31 32KHZ Type Reset RO 1 15 30
reserved
29 CCP5 RO 1 13
28 CCP4 RO 1 12
27 CCP3 RO 1 11
reserved
26 CCP2 RO 1 10
25 CCP1 RO 1 9
24 CCP0 RO 1 8 C0O RO 1
23
22
21 reserved
20
19
18 ADC2
17 ADC1 RO 1 1
16 ADC0 RO 1 0
RO 0 14
RO 0 7
RO 0 6
RO 0 5
RO 0 4
RO 0 3
RO 1 2
reserved Type Reset RO 0 RO 0
C2PLUS C2MINUS RO 1 RO 1
C1PLUS C1MINUS RO 1 RO 1
C0PLUS C0MINUS RO 1 RO 1 RO 0 RO 0
reserved RO 0 RO 0 RO 0 RO 0
RO 0
Bit/Field 31
Name 32KHZ
Type RO
Reset 1
Description 32KHz Input Clock Available When set, indicates an even CCP pin is present and can be used as a 32-KHz input clock.
30
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. CCP5 Pin Present When set, indicates that Capture/Compare/PWM pin 5 is present.
29
CCP5
RO
1
28
CCP4
RO
1
CCP4 Pin Present When set, indicates that Capture/Compare/PWM pin 4 is present.
27
CCP3
RO
1
CCP3 Pin Present When set, indicates that Capture/Compare/PWM pin 3 is present.
26
CCP2
RO
1
CCP2 Pin Present When set, indicates that Capture/Compare/PWM pin 2 is present.
25
CCP1
RO
1
CCP1 Pin Present When set, indicates that Capture/Compare/PWM pin 1 is present.
24
CCP0
RO
1
CCP0 Pin Present When set, indicates that Capture/Compare/PWM pin 0 is present.
23:19
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. ADC2 Pin Present When set, indicates that ADC pin 2 is present.
18
ADC2
RO
1
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System Control
Bit/Field 17
Name ADC1
Type RO
Reset 1
Description ADC1 Pin Present When set, indicates that ADC pin 1 is present.
16
ADC0
RO
1
ADC0 Pin Present When set, indicates that ADC pin 0 is present.
15:14
reserved
RO
0
Software should not rely on the value of a reserved bit. [. . . ] 100-Pin LQFP Tape and Reel Dimensions
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IMPORTANT NOTICE
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